1. Field of the Invention
The subject matter of the present invention pertains to computer systems, and more particularly, to an arbitration mechanism which resolves priority of access to a shared bus based on a rotating priority scheme, the scheme being selectively changeable by the user.
2. Description of the Prior Art
In a computer system, various processors and input/output units disposed within the computer system may require access to a common shared data bus at approximately the same time. However, the data bus can handle only one access at a time. Therefore, some mechanism must be utilized to determine which unit and which processor may be granted access to the bus.
Various arbitration mechanisms have been utilized by prior art computer systems. In an article entitled "Performance Analysis of High Speed Digital Buses for Multiprocessing Systems" by W. L. Bain and S. R. Ahuja, Bell Laboratories, Murray Hill, N.J., several arbitration mechanisms are discussed. For example, the article discusses the Static Priority Algorithm, the Fixed Time Slice Algorithm, Dynamic Priority Algorithms including the Least Recently Used Algorithm and the Rotating Daisy Chain Algorithm, and the First Come First Served Algorithm. This article is incorporated by reference into the specification of this application.
Most of the above identified prior art arbitration mechanisms arbitrate based on a fixed priority in descending order. None take into account the following special features: dual level input/output (I/O) requests for preventing I/O timeouts, a rotating, selectively changeable, highest priority at all I/O levels for preventing I/O lockouts, processor bus operation cycle steal requests for preventing processor lockouts, an instruction cache preemptive grant which saves one arbitration cycle, data cache inpage and castout operation in one cycle which saves one arbitration cycle, and Processor Bus Operation (PBO) grants during refresh for utilizing otherwise wasted cycles.
U.S. Pat. No. 4,449,183 to Flahive et al discloses a mechanism for granting access to a shared bus on a "rotating priority basis". However, the arbitration scheme discussed in this patent resembles the rotating daisy chain algorithm referenced above. There is no discussion of the above mentioned special features.